This invention generally relates to semiconductor integrated circuit (SIC) devices that make use of logic elements formed of CMOS devices. More specifically, the present invention pertains to a SIC device with a desirable form achieved by controlling, even when light refractlon/interference in lithography processing or "grounding" in etching processing occurs due to the advance of miniaturization in the LSI fabrication, the effect of such occurrence.
Several ways of implementing a CMOS logic section for semiconductor integrated circuits, such as gate array architecture, standard cell architecture, and custom layout architecture, have been known in the art (see "The Design of ULSIs," published by Kikaku Center and "The Design of CMOS ULSIs," published by Baifu-Kan). A conventional CMOS logic section is provided with a desirable logic circuit as follows. According to a logic circuit to be implemented, n-channel and p-channel transistors, which each have a rectangular source diffusion region, gate region, and drain diffusion region, are laid out and interconnections are provided by forming polysilicon layers and interconnection layers (metal layers), to implement a target logic circuit,
SIC devices are completed by the following steps: (i) the design step for producing a mask pattern by carrying out, based on the specifications of a target SIC device, functional design, logic design, and mask design, (ii) the mask production step for producing a photomask from the mask pattern prepared in the design step, (iii) the LSI fabrication step for forming, by making utilization of the photo mask prepared in the mask production step, circuitry on a silicon substrate by means of oxidation, diffusion, lithography, etching, CVD, sputtering, and so on, (iv) the assembly step for carrying out packaging, and (v) the inspection step for testing whether SIC devices completed are functioning correctly.
For the case of SIC devices employing therein a conventional CMOS logic section, mask patterns, prepared in the design step for transistors formed of a rectangular source diffusion region, gate region, and drain diffusion region, are classified to mask layers required in the LSI fabrication step and thereafter are converted into patterns of rectangles on a photomask. The photomask thus created is used to fabricate a target SIC device.
With the advance of miniaturization, in the LSI fabrication of SIC device circuits of the deep sub-micron generation in which the gate length is 0.25 .mu.m or less, due to light interference or proximity effect in the lithography process and due to the mask form dependency in the etching process, there may be produced a considerable difference in form between a mask pattern prepared in the design step and a form produced on a post-LSI fabrication SIC device. The resulting SIC device is therefore problematic, in other words it may suffer electrical characteristic problems and will not operate correctly.
To cope with such a problem, in the development of LSI fabrication after the deep sub-micron generation, a plurality of mask patterns of various forms different from the form of a target SIC device, are prepared. Such mask patterns are experimentally produced in an LSI fabrication step or subjected to photolithography simulation carried out by computer, in order to obtain a mask pattern form capable of implementing a SIC device with a form most similar to the target form. In the mask production step, based on characteristics obtained from the mask pattern form, special mask correcting processes, such as the adjustment of linewidth and the addition of smaller rectangles to vertices of each rectangle, are performed on a mask pattern portion at which the foregoing effects such as the interference of light are expected to take place. For the proximity effect, a phase shift technique has been proposed wherein the polarizing directions of adjacent mask patterns are arranged in such a way as to cross at right angles. Photolithography technologies for use in post-deep sub-micron generation LSI fabrication are shown by T. Takigawa and others, "ULSI Lithography Technology Innovaton," published by Science Forum.
However, SIC devices according to conventional technology suffer various problems. Since conventional SIC devices are fabricated by combinations of rectangular figures of various sizes and by means of mask patterns, the effect of lithography and etching processing due to miniaturization is very complicated. For this reason, it is hard in the LSI fabrication to experimentally produce a mask pattern capable of producing a desirable semiconductor integrated circuit device form. The foregoing simulation may be completed in a realistic period of time when only several transistors are involved; however, it is very difficult to estimate and find all possible patterns for a SIC device fabricated by integration of several millions of transistors in various forms.
In the phase shift technology, it is required to perform allocation of phases orthogonal to mask patterns adjacent to each other. Since conventional SIC devices are designed using rectangular figures of various forms, this is a bar to suitably allocating phases.